A. Field of the Invention
The present invention relates to a MASH structure of sigma-delta modulators. More specifically, the present invention relates to a cascade of discrete-time differentiators which can be used within a MASH structure of sigma-delta modulators.
B. Problems in the Art
The use of a MASH structure of sigma-delta modulators is known in the art for fractional-N frequency synthesis. The role of sigma-delta modulation, as used in frequency synthesis, is to provide a means for fractional frequency resolution and to shape a resultant noise power density out of a desired frequency spectrum. An example of the use of a MASH structure of sigma-delta modulators is disclosed in U.S. Pat. No. 5,038,117, the disclosure of which is hereby incorporated by reference in its entirety. It is understood that increasing the order of the noise shaping function by increasing the number of sigma-delta modulators in the MASH structure is useful for reducing the quantization noise within the frequency spectrum of interest.
There are MASH structure designs currently in the art which can successfully implement low-order noise-shaped sigma-delta modulation. However, as the order of the noise shaping function is increased, latency problems prevent the prior art structures from being implemented successfully. In this context, there are two types of latency associated with the differentiators in the MASH structure. The first type is a time delay due to the insertion of a flip-flop in the signal path. A flip-flop circuit delays an incoming signal by one sample period. The second type of latency is propagation delay. Propagation delay is primarily due to two components. The first component is due to the limited bandwidth of the semiconductor process. The second component is related to the number of circuit functions, such as adders, that a signal must propagate through. While the semiconductor process is generally fixed for a given application, the circuit configuration can be modified to compensate for the semiconductor process being targeted.
One method of compensating for propagation delay is to insert unit delay functions within the critical signal path of the differentiators. The insertion of unit delay requires additional hardware and causes the signal being processed to be shifted in phase. When sigma-delta modulation is used in a control loop such as a phase-locked loop, this additional phase shift leads to instability. To compensate for such instability, the bandwidth of the control loop must be reduced. In many cases, bandwidth reduction is undesirable due to a corresponding reduction in the agility of the control loop.
The present invention discloses a method and apparatus which overcomes the latency problems associated with higher order noise shaping in MASH structures without using additional unit delays. By characterizing the transfer function of a discrete-time differentiator in the z-domain, expressing the z-domain transfer function of a cascade of multiple discrete-time differentiators as a polynomial in z, expanding the polynomial in z using Horner""s Rule, and implementing the resultant structure in hardware, an improved MASH structure of sigma-delta modulators can be constructed. By implementing a design based on the expanded form of the polynomial expression and utilizing implicit multiplication, a high-order MASH structure of sigma-delta modulators can be implemented that does not exhibit the latency problems associated with prior art.
Although the present invention will be discussed primarily with respect to higher order MASH architectures, it will be readily apparent to those skilled in the art that the design methodology can be extended to low-order MASH architectures as well. Therefore, the present invention is not intended to be limited simply to high-order MASH architectures, but applies to a MASH structure of sigma-delta modulators in general, and more specifically to a cascade of discrete-time differentiators which can be used within the MASH structure of sigma-delta modulators.
C. Features of the Invention
A primary feature of the present invention is a method for implementing a high-order MASH structure of sigma-delta modulators which reduces latency problems in the prior art.
Another feature of the present invention is a high-order MASH structure of sigma-delta modulators which operates at higher speeds than those known in the prior art.
Another feature of the present invention is a MASH structure of sigma-delta modulators which is implemented by realizing the z-domain transfer function of a cascade of multiple differentiators as an expanded polynomial expression using Horner""s Rule.
Another feature of the present invention is a cascade of multiple discrete-time signal differentiators that utilize implicit multiplication in an adder to realize coefficients.
Another feature of the present invention is a cascade of multiple discrete-time signal differentiators that use two""s complement number representation to realize negative coefficients.
Another feature of the present invention is a cascade of multiple discrete-time signal differentiators wherein a signal must propagate through only one circuit function per sample period.
Another feature of the present invention is a MASH structure of sigma-delta modulators which can be used to control a frequency divider or a phase-locked loop.
Yet another feature of the present invention is a cascade of multiple discrete-time signal differentiators wherein the input signal is input in multiple places in the differentiator.
These, as well as other features of the present invention, will be apparent from the following detailed description and claims in conjunction with the accompanying drawings.
A method to reduce latency in an n""th order differentiator includes characterizing the z-domain transfer function of a cascade of multiple discrete-time differentiators according to a polynomial expansion using Horner""s Rule. Realizing the expanded form of the polynomial expression in hardware reduces latency.
An n""th order differentiator comprises at least one latch and at least one adder, each having an input, with all adder inputs arranged in parallel. The bit-position inputs at the adders are determined according to the coefficients of the z-domain polynomial transfer function of the differentiator.
A method to reduce latency in a phase-locked loop frequency synthesizer that includes a MASH structure of n sigma-delta modulators having n accumulators comprises implementing an expanded polynomial z-domain transfer function for each of the n differentiators in the MASH structure.
A MASH structure of n sigma-delta modulators is realized by implementing the n differentiators within the MASH structure according to the expansion of the z-domain polynomial transfer function of a cascade of multiple discrete-signal differentiators using Horner""s Rule.